The unit is the time-based licence sold to a design team: a bundle of tools for "generally two to three years", invoiced in equal quarters and recognised evenly over the term. Each booking enters backlog, now $8.1B with 58% due within 12 months, against FY2025 revenue of $5.30B.
Extra licences cost almost nothing to deliver, so gross margin is 86%. The real cost is people, and those costs are largely fixed, so the business earns about 45% non-GAAP and 28.2% GAAP operating margin and converts about 30% of revenue into free cash flow.
| What it is | Software, emulation hardware and silicon IP used to design, verify and sign off chips, boards and systems before anything is built. |
|---|---|
| Industry | Electronic design automation (EDA) and semiconductor IP, a three-vendor oligopoly at its core, plus a newer position in engineering simulation. |
| How it makes money | Multi-year licences recognised over time (78% of revenue recurring in Q2 2026), plus upfront hardware, IP and simulation licences. |
| What protects it | Foundry-certified signoff flows, methodologies embedded in customers' teams, and a $1.77B R&D budget only two rivals can match. |
| What drives earnings | The number and complexity of advanced design projects; attach of hardware and IP; acquired expansion into system simulation. |
| Cycle exposure | Low to medium. Revenue rose every year from 2016 to 2025. The cyclical part is the 22% recognised upfront. |
A chip is designed, simulated and checked against the foundry's manufacturing rules entirely in software before a mask is made, because an error found in silicon means a costly re-spin and months of lost time. Cadence sells the tools for that work: circuit design (Virtuoso, Innovus), verification (Xcelium, Jasper, Palladium emulators and Protium prototyping), silicon IP blocks, and analysis tools for packages, boards and whole systems (FY2025 10-K). Demand follows the number of design projects customers start, not the number of chips they ship.
Revenue sits in three categories with different mechanics. Core EDA (70% of FY2025 revenue) is mostly ratable software plus emulation hardware sold upfront. Semiconductor IP (14%) is licensed per design and recognised on delivery, with $87.3M of royalties in FY2025. System Design and Analysis (16%) covers boards, packages, thermal and fluid analysis, and since 2024 structural simulation; its longer licences are recognised upfront. No customer reached 10% of revenue in FY2023 to FY2025.
The mix is moving away from pure ratable software. Recurring revenue was around 90% in 2016, 84% in 2023, 80% in 2025 and 78% in Q2 2026, because hardware, IP and simulation licences, all recognised upfront, grew faster. Those lines cost more to deliver: hardware manufacturing costs rose to $376.6M in FY2025 from $232.0M in FY2023 (FY2025 10-K, Note 21). Cadence publishes no seat count or licence price, so the unit can be described but not priced (unknown).
The industry sells certainty that a design will work and can be manufactured. Electronic system design revenue was $5.75B in Q1 2026, up 12.7% (SEMI ESD Alliance, web), and the four 2025 quarters sum to roughly $21B, under 3% of the $795.6B of 2025 chip sales (WSTS, web; inferred). A cost that small, attached to a decision as costly as a failed tape-out, is the root of the industry's pricing power.
The market is global and concentrated: TrendForce put 2024 EDA shares at 31% Synopsys, 30% Cadence and 13% Siemens (web). Three barriers bind. Cadence co-develops process design kits with foundries so its tools meet signoff at each new node; customer scripts, flows and trained engineers make switching a multi-year project risk; and R&D of $1.77B in FY2025 is a budget only two rivals can match. China shows how high the bar is: state-backed funding has produced a domestic leader, Empyrean, with RMB 502M of revenue in the first half of 2025, against $680M of Cadence revenue in China in FY2025.
Cadence and Synopsys diverged in 2025. Synopsys's Design IP segment fell 8% and its adjusted margin dropped from 38% to 24%, while its China revenue fell 22% excluding Ansys (Synopsys FY2025 10-K). Cadence's China revenue rose 19% and its IP share rose from 13% to 14%. In system simulation Cadence is the challenger: it bought BETA CAE ($1.14B net, 2024) and Hexagon's design and engineering business (D&E, $2.9B net, February 2026) to compete with Ansys inside Synopsys, which cost $34.9B, and Siemens with Altair, about $10B.
The kind of company that wins in core EDA has a full, foundry-certified flow at the leading node and the R&D budget to redo it every node. Cadence is that kind of company in chip design. In system simulation it has not yet shown it is, and NVIDIA's $2B stake in Synopsys (December 2025, Bloomberg Law, web) signals that the largest AI chip designer has picked a preferred partner.
Revenue grew from $1.82B in 2016 to $5.30B in 2025, a 12.6% compound rate, and 14.6% a year from 2020. Cadence does not split growth into price and volume or report organic growth. For FY2025 it called acquisitions not material, so 14.1% reported growth was close to organic. In 2026 Hexagon D&E changes that, and the pro forma figures in the Q2 2026 10-Q allow a split.
| Period | Reported | Pro forma | Acquired effect |
|---|---|---|---|
| Q2 2026 vs Q2 2025 | 24.2% | 17.5% | 6.7 pts |
| H1 2026 vs H1 2025 | 21.5% | 16.7% | 4.8 pts |
| FY2026 guidance midpoint | 19% (incl. D&E) | ~12% (excl. D&E) | ~7 pts |
Larger chips, chiplets and 3D stacking need more verification cycles and emulation capacity. Hardware manufacturing costs rose 62% from FY2023 to FY2025, a proxy for hardware volume (inferred).
IP rose from 11% of revenue in 2016 to 15% in H1 2026, helped by bought-in Rambus and Arm Artisan IP. Synopsys's 2025 stumble is a tailwind that may not last.
System Design and Analysis grew from 10% of revenue in 2016 to 17% in Q2 2026, mostly by acquisition. D&E adds roughly $316M a year (inferred from about $158M in H1 2025 pro forma).
Hyperscalers and automakers are named as customers, but no revenue split is disclosed, so this driver is asserted, not measured.
13% of FY2025 revenue and 15% of Q2 2026, with 2026 growth inflated by the depressed 2025 base. Price is the unranked sixth driver: rising backlog and stable gross margin are consistent with pricing power, but no filing quantifies it.
Salaries and benefits of $2.13B plus $455M of stock compensation made up 49% of FY2025 revenue, and the company calls these costs "relatively fixed in the short term". Margin therefore expands when revenue outgrows headcount: GAAP operating margin rose from 13.5% in 2016 to 30.6% in 2023 as R&D fell from 40.5% to 35.3% of revenue. Since then it slipped to 28.2%, or 30.6% before the $128.5M export-control charge, because lower-margin hardware and services grew, acquisition amortization rose and stock compensation reached 8.6% of revenue.
| FY2016 | FY2020 | FY2023 | FY2025 | |
|---|---|---|---|---|
| Revenue ($M) | 1,816 | 2,683 | 4,090 | 5,297 |
| Gross margin | 85.9% | 88.6% | 89.4% | 86.4% |
| GAAP operating margin | 13.5% | 24.1% | 30.6% | 28.2% |
| R&D, % of revenue | 40.5% | 38.5% | 35.3% | 33.4% |
| Free cash flow ($M) | 391 | 810 | 1,247 | 1,587 |
| Diluted shares (M) | 291.3 | 279.6 | 272.7 | 273.3 |
Cash conversion is strong: FY2025 operating cash flow of $1.73B exceeded net income of $1.11B because stock compensation is non-cash and customers are billed ahead of ratable revenue, and capex was $142M. The $140.6M penalty paid and roughly $151M of cash tax saved by restored R&D expensing roughly offset each other.
From 2016 to 2025 Cadence produced $8.92B of free cash flow and spent it on buybacks ($5.83B), acquisitions ($2.59B in cash plus $0.50B in stock for BETA CAE) and no dividends. The buyback mostly neutralised employee equity: against $2.44B of stock compensation it cut diluted shares only 6%, from 291.3M to 273.3M, and the D&E shares lifted the count back to 276.2M. In February 2026 management paid $2.2B in cash plus 3.2M shares worth $902M for D&E, the largest deal in the ten-year record, moving from net-cash buybacks to levered acquisitions while still planning to return about half of 2026 free cash flow. The bonus pays on revenue and non-GAAP operating margin, so neither amortization nor stock compensation weighs on it (inferred).
Cadence sells into customers' R&D budgets, not their unit volumes. In 2023, when global chip sales fell 8.2% (SIA, web), Cadence revenue grew 14.8%; the industry is not immune, as EDA revenue fell 9.5% on a four-quarter average through 2009 (EDA Consortium, web). Today the business sits at its cyclical high on volume and mix: 2026 revenue is guided to a record $6.26B to $6.34B, backlog is a record, and upfront revenue is 22% of the total. Margins are near but not at peak: H1 2026 GAAP margin of 28.8% is below 2023's 30.6%.
A pause in AI spending would hit the upfront slice first: fewer large-chip projects would cut emulation hardware and IP orders, while the 78% ratable base kept flowing from backlog. With costs largely fixed, that fall would drop almost straight to operating income. The binding constraints are regulatory: Cadence pleaded guilty in July 2025 to conspiracy to violate export controls and is on three years' probation, and a BIS rule extending restrictions to 50%-owned affiliates is suspended only until 9 November 2026.
| Exposure | Share of FY2025 revenue |
|---|---|
| Core EDA / Semiconductor IP / System Design and Analysis | 70% / 14% / 16% |
| United States | 44% |
| Other Asia | 19% |
| Europe, Middle East and Africa | 15% |
| China | 13% |
| Japan | 6% |
| End market (AI, mobile, auto, industrial) or customer type | Not disclosed |
| Indicator | Why it matters | Where published |
|---|---|---|
| Backlog and share due in 12 months | Leads revenue; would weaken before revenue does | 10-Q Note 3 |
| Recurring vs upfront revenue | How much depends on hardware and IP timing | 10-Q MD&A |
| China revenue and US export rules | One rule change cut deliveries in 2025; affiliates rule suspended to 9 Nov 2026 | 10-Q geography table; BIS notices |
| GAAP vs non-GAAP margin; amortization | Whether D&E earns its price or dilutes margin | Quarterly release and CFO commentary |
| IP share vs Synopsys Design IP | Whether 2025 gains are share or a rival's stumble | CDNS 10-Q; SNPS 10-Q segment note |
| ESD industry growth by category | Independent read on tool and IP demand | SEMI ESD Alliance EDMD, quarterly |
| Stock compensation and diluted shares | How much cash goes to offsetting dilution | 10-Q cash flow and EPS note |
The sources could not answer: price versus volume; renewal and churn rates; hardware revenue and margin; revenue by end market or customer type; organic growth before 2026; D&E standalone margin and growth; Siemens EDA financials and independent share data in analog and emulation.
Questions before a thesis: how much of the 2025 to 2026 hardware and IP strength is AI-capex timing; whether D&E reaches Cadence-level margins or holds non-GAAP margin below 45%; and how agentic AI tools will be priced.