Business Overview

Taiwan Semiconductor Manufacturing Company (TSM / 2330.TW)

6 September 2026

Evidence base: ten Form 20-F annual reports (FY2016–FY2025, latest filed 16 April 2026) and 434 Form 6-K

filings held in the research folder; supplemented by TSMC’s Q1 and Q2 2026 primary investor disclosures and by

independent industry sources (TrendForce, Counterpoint, SIA, WSTS, SEMI, IDC) and competitors’ own reporting.

This is not a valuation and not a recommendation.

1. Executive Snapshot

2. What the Company Does

Designing a modern chip and manufacturing one are different businesses requiring different assets. A company that designs a phone processor needs a few hundred engineers and software licences. A company that manufactures it needs a factory costing tens of billions of dollars, a decade of process research, and enough volume across many customers to keep that factory full. TSMC exists because those two activities separated. It builds the factory and sells access to it, so that Apple, Nvidia, AMD, Qualcomm and Broadcom never have to.

The unit of economics is one 12-inch-equivalent wafer. A wafer is a polished silicon disc roughly 300mm across. TSMC receives the customer’s circuit design, translates it into photomasks, and then runs the wafer through several hundred process steps — deposition, lithography, etching, implantation — that build transistors and their wiring layer by layer. A single wafer takes roughly three months to traverse a leading-edge fab. It emerges carrying anywhere from a few dozen to several thousand identical chips, depending on how large each chip is. The customer is billed for the wafer, not for the working chips on it, which is why yield is the customer’s problem as well as TSMC’s and why a foundry with better yield can charge more per wafer and still be cheaper per working chip.

Tracing one wafer to cash: the customer commits capacity months ahead, sometimes with prepayments — TSMC held NT$189.9bn of temporary receipts from customers at the end of FY2025 (FY2025 20-F). The wafer is processed, tested, and in many cases packaged; TSMC then bills, and collected in an average of 29 days in Q2 2026 (TSMC 2Q26 management report). Cash therefore arrives quickly. What arrived years earlier was the capital: the equipment that processed the wafer was bought in an earlier cycle and is depreciated over five years for machinery, a life unchanged across every filing from FY2016 to FY2025.

Price per wafer is set almost entirely by which process node runs it. FY2025 wafer revenue split 24% at 3nm, 36% at 5nm, 14% at 7nm, 7% at 16nm and 7% at 28nm, with everything at 7nm and below — what TSMC calls advanced technologies — reaching 74% of wafer revenue, up from 69% in FY2024 and 58% in FY2023 (FY2025 20-F). By Q2 2026 that aggregate was 77%, with 2nm broken out for the first time at 3% of wafer revenue (TSMC 2Q26 earnings release). This is the whole business model in one line: TSMC is not selling more wafers so much as selling more expensive ones.

The remaining 14% of revenue comes from packaging and testing, mask making, design services and royalties (FY2025 20-F). Packaging has changed in character. It was once a low-value back-end step, and TSMC reclassified it out of wafer revenue in 2017 (FY2017 20-F), which is why the wafer-fabrication share of revenue appears to drop from roughly 96% to 89% that year without anything real happening. Advanced packaging — CoWoS, SoIC, InFO — is now a bottleneck rather than a commodity: TSMC allocates 10–20% of its 2026 capital budget to advanced packaging, testing and mask making, and its CEO said on the Q2 2026 call that “our packaging capacity is so tight that now it’s limiting my customers’ growth.” TSMC does not disclose CoWoS capacity or its revenue contribution (unknown).

TSMC is not exiting product lines in the ordinary sense, because it does not have products. What it is doing is letting mature capacity shrink as a share of the mix while adding leading-edge capacity. Nodes at 40nm and above fell from 21% of wafer revenue in FY2023 to 12% in FY2025 (FY2025 20-F). Those nodes are not unprofitable — they run on equipment long since depreciated — but they no longer absorb capital. Separately, in May 2026 TSMC agreed to sell up to 152.0 million shares of Vanguard International Semiconductor, cutting its stake from roughly 27.1% to about 19%, explicitly to focus resources on the core business (6-K 2026-05-15).

3. Industry, Competitive Position & Moat

The foundry industry exists because the cost of a leading-edge fab rose faster than any single chip designer’s volume. Independent Business Strategies estimated a 50,000-wafer-per-month 2nm fab at roughly US$28bn against about US$20bn at 3nm (IBS, cited December 2023 — dated, and no more recent independent estimate was found). SEMI projects US$133bn of 300mm fab equipment spending in 2026, rising to US$151bn in 2027 (SEMI, 1 April 2026). At that scale, only a manufacturer aggregating demand from hundreds of designers can keep a fab full, and only a full fab earns a return.

The industry is extraordinarily concentrated and became more so through 2025. TrendForce puts full-year 2025 top-ten foundry revenue at US$169.5bn, with TSMC at US$122.5bn and 69.9% share, Samsung Foundry second at 7.2% on revenue that fell 3.9%, and SMIC third at 5.3% (TrendForce, 13 March 2026). Counterpoint reads TSMC at 73% in Q2 2026 (Counterpoint, 26 August 2026). The leading-edge segment is more concentrated still: Counterpoint puts TSMC above 86% of foundry share at 5nm and below, though that figure is anchored on smartphone SoCs specifically, and a clean all-segment leading-edge split by vendor could not be sourced (unknown).

Where the profit pool sits

Ranking the value chain by the most recent reported operating margin makes the structure legible. Nvidia, the fabless designer of the scarce accelerator, earned a 66.2% operating margin in its July 2026 quarter. TSMC earned 60.3% in Q2 2026. ASML, a genuine equipment monopoly in EUV lithography, reported a 54.0% gross margin, and Applied Materials a 33.7% operating margin. Amkor, an outsourced assembly and test provider, earned 10.5%. The instructive comparison is inside the foundry layer itself: GlobalFoundries earned 9.7% and UMC 21.8% on the same business model in the same quarter. TSMC’s 60% is not a foundry rent. It is a leading-edge scarcity rent that only one foundry currently collects.

Margins as reported by each company. ASML is omitted from the operating-margin column because it guides on gross margin: 54.0% in Q2 2026 against 2026 guidance of 54–56%.

Which barriers actually bind

Several barriers are merely expensive, and money solves them. Fab capital is one: Japan has funded Rapidus with JPY 267.6bn from the state and 32 private companies toward 2nm production in 2027 (Rapidus, 27 February 2026), and the United States took a 9.9% equity stake in Intel for US$8.9bn in August 2025. EUV tool access is another — binding but purchasable, since ASML is raising Low-NA EUV capacity by 30% for 2027 and shipping roughly 65 units in 2026 (ASML Q2 2026 call). The exception is China, where EUV is unavailable at any price, which is why SMIC remains capped at 7nm with a reported sub-20% yield on a 5nm-class pilot line.

Two barriers money does not solve. The first is yield learning. Samsung’s 2nm yield was reported by Korean media at roughly 55% against TSMC’s 80–90% (April 2026), below the level analysts put at the threshold of profitability; TrendForce reported 55–60% in November 2025, and a February 2026 trade claim of 70% remains unconfirmed. Samsung has spent at scale for a decade and its foundry share still fell in 2025. Yield is accumulated defect-and-process learning against real production volume, and volume is precisely what a challenger cannot get until its yield is good. The second is customer qualification. Intel has 18A in production, a sovereign shareholder, and High-NA EUV before anyone else — and as of January 2026 had two prospective 14A customers and zero committed, with decisions running into 2027 and volume production not before 2028 (Tom’s Hardware, 23 January 2026). A design win is a two-to-four-year commitment made against a yield history the challenger does not yet have.

TSMC’s specific position

What would be hardest for a well-funded competitor to reproduce is not any single asset but the compounding loop between them. TSMC’s FY2025 R&D of NT$246.4bn was funded out of NT$2,275.0bn of operating cash flow, so process development is self-financing rather than a call on the balance sheet (FY2025 20-F). That research produces the node that wins the design, the design brings the volume, the volume produces the yield data, and the yield funds the next node. A challenger must enter this loop at its weakest point and fund the gap from elsewhere — which is exactly what Intel Foundry’s US$2.1bn quarterly operating loss represents.

Two structural assets support the loop. TSMC competes with no customer, which matters when Samsung both fabricates for and competes against phone makers. And the Taiwan cluster is dense enough that TSMC can, in its own words, “temporarily reassign thousands of our engineers and other relevant personnel from one manufacturing site to another” (FY2025 20-F) — a flexibility the company itself flags as at risk in its overseas fabs.

A third asset has emerged more recently. Advanced packaging is now a second chokepoint alongside the transistor. TrendForce puts TSMC CoWoS capacity at 120,000–140,000 wafers per month in 2026 plus 50,000–60,000 from OSAT partners, with the supply-demand gap narrowing from roughly 20% to 10% by end-2026 and capacity rising a further 60% in 2027 (TrendForce, 15 June 2026). CoWoS wafer ASPs are reported approaching 7nm levels (TrendForce, 28 April 2026). Controlling both the transistor and the package is a materially stronger position than controlling either alone.

What could weaken it

Three things, in order of how quickly they could bite. Samsung’s 2nm yield could be independently confirmed above the profitability threshold, which would give a second source to customers who want one — Tesla has already committed US$16.5bn to Samsung’s Taylor, Texas fab (July 2025). Intel could convert a 14A prospect into a signed commitment; a preliminary, unsigned Apple–Intel foundry arrangement for entry-level M-series parts was reported in May 2026. And TSMC’s own overseas expansion mechanically weakens the cluster advantage it depends on, because a fab in Arizona or Dresden cannot borrow engineers from Hsinchu.

The outside evidence answers the question of what kind of company wins here, and it is not the best-capitalised one. Samsung has memory profits, Intel has a sovereign shareholder, and Rapidus has Tokyo; none has converted capital into leading-edge share. What separates the winner is yield at volume and the customer trust that yield history buys. TSMC is that kind of company — which is also a warning, because the same evidence says the position is defended by an operating record, not by a legal or physical barrier.

4. Growth Engine

All of TSMC’s growth over the past decade is organic. A review of all ten annual reports found no material acquisition in the FY2016–FY2025 period. Goodwill has been effectively frozen for nine years — NT$6,105m in 2015, NT$5,791.8m of cost basis at end-2024 — and the FY2016 filing attributes the only movement to exchange rates. The two new offshore entities in the window, JASM in Japan (December 2021) and ESMC in Germany (June 2023), were established rather than acquired: TSMC is the controlling founder and Sony, DENSO, Bosch, Infineon and NXP bought minority stakes into TSMC’s vehicles. That is inbound minority capital, not outbound M&A. Reported growth and organic growth are therefore the same number, and no decomposition between them is required.

The decomposition that does matter is volume against price and mix. Between FY2016 and FY2025, net revenue rose 4.02 times while wafer shipments rose only 1.56 times. Revenue per 12-inch-equivalent wafer therefore rose 2.57 times, from roughly NT$98.7 thousand to NT$253.6 thousand (inferred from the revenue and shipment figures in each year’s 20-F). On a logarithmic basis that makes price and mix roughly two-thirds of the decade’s growth and volume roughly one-third. The FY2022-to-FY2024 stretch makes the point starkly: shipments fell 15% from 15,253 thousand wafers to 12,910 thousand while revenue rose 28%.

Revenue per wafer and the growth shares are inferred, computed from net revenue and wafer shipments as reported in the FY2016 and FY2025 20-Fs. Packaging and testing revenue was reclassified out of wafer revenue in 2017 (FY2017 20-F), so FY2016 is on a marginally different basis; the direction and magnitude are unaffected. TSMC has never disclosed an absolute average selling price per wafer (unknown).

Drivers, ranked

• AI and high-performance computing demand — structural in direction, cyclical in magnitude. HPC contributed NT$716.0bn of FY2025’s revenue increase, a 48$660–690bn in 2026 (company guidance compiled February–July 2026), which is a budget decision by five buyers, not a structural constant.
• Node migration — structural. Each node transition raises the price of a wafer because the customer is buying transistor density, not silicon. Advanced technologies at 7nm and below went from 58% of wafer revenue in FY2023 to 74% in FY2025 and 77% in Q2 2026. This driver operates whether or not AI demand persists, so long as TSMC keeps process leadership; it is the reason revenue per wafer rose through the FY2023 downturn.
• Advanced packaging scarcity — temporary, becoming structural. CoWoS capacity is short of demand by roughly 20%, narrowing to 10% by end-2026 (TrendForce, 15 June 2026), and packaging wafer ASPs are reported near 7nm levels. Scarcity rent decays as capacity arrives — 60% more in 2027 — but the capability itself is becoming a permanent part of the moat.
• Mature-node repricing — cyclical, and running opposite to expectation. Rather than Chinese capacity deflating trailing-edge prices, TrendForce documents mature-node price increases of 5–15% between Q1 and Q2 2026 and a further 5–10% into Q3, driven by TSMC and Samsung cutting 8-inch and 12-inch mature capacity while AI power-management demand rises (TrendForce, 30 June 2026). This is a favourable turn in a segment that had been the drag.
• Geographic expansion — management-driven, and margin-negative. Arizona, Kumamoto and Dresden add capacity that customers and governments want, but at a structurally higher cost. This driver adds revenue and subtracts margin; it is quantified in Section 5.

TSMC guided full-year 2026 revenue growth to “slightly above 40% year over year in US dollar terms” on the Q2 2026 call, raised from above 30% three months earlier. Monthly revenue supports it: July 2026 net revenue of NT$467.6bn was up 44.7% year over year, the fastest print in the series (6-K 2026-08-10).

5. Margin, Cash & Capital Allocation

TSMC’s margin structure follows from owning its factories. In its own words, “because we own most of our manufacturing capacities, a significant portion of our operating costs is fixed. In general, these costs do not decline when customer demand or our capacity utilisation rates drop” (FY2025 20-F). Depreciation and amortisation of NT$688.1bn in FY2025 was 18% of revenue and is largely insensitive to volume. Operating leverage therefore runs hard in both directions: gross margin was 46.0% in FY2019 and 67.7% in Q2 2026 on a cost base that changes far more slowly than revenue does.

Management attributes the FY2025 gross margin improvement to 59.9% from 56.1% to “higher capacity utilisation and cost improvement, partially offset by unfavourable foreign exchange rate” (FY2025 20-F). Currency is a first-order variable, not a footnote: TSMC quantifies that every 1% depreciation of the US dollar against the New Taiwan dollar costs approximately 0.3 percentage points of operating margin, because substantially all sales are in US dollars while a large part of the cost base is not.

Operating expenses have fallen as a share of revenue — from 11.8% in FY2023 to 9.1% in FY2025 — but this is denominator arithmetic, not restraint. R&D spending rose 20.7% in FY2025 to NT$246.4bn, directed at 10-, 14- and 16-angstrom process research; it simply grew more slowly than a 31.6% revenue increase. R&D at 6.5% of revenue is the lowest ratio in the decade and the highest absolute figure.

The financial spine

Years chosen to show the shape of the change, not every year available. Comparability caveats: packaging and testing revenue was reclassified out of wafer revenue in 2017, so FY2016 revenue per wafer sits on a marginally different basis; TSMC redefined “advanced technologies” twice over this period (28nm-and-below through FY2018, 16nm-and-below in FY2019–FY2020, 7nm-and-below thereafter), so that ratio is not continuous and is excluded here; IFRS 16 was adopted in 2019, adding right-of-use assets absent before. Headline revenue, gross profit, operating income and net income cross-check cleanly across filings with no restatement. Revenue per wafer and capex ratios are inferred.

The table shows a business that got more capital-hungry through the 5nm and 3nm build-out and is now, briefly, growing faster than its capital budget. That reversal is unlikely to persist: TSMC raised its FY2026 capital budget to US$60–64bn on the Q2 2026 call, from the US$52–56bn stated in the FY2025 20-F. Against guided revenue growth slightly above 40%, capital intensity rises again in 2026, and the depreciation from that spending arrives over the following five years — the machinery useful life has been five years in every filing across the decade.

Cash conversion

Conversion is unusually clean for a capital-intensive manufacturer. FY2025 operating cash flow of NT$2,275.0bn against net income of NT$1,697.6bn reflects the large non-cash depreciation charge. Capital expenditure of NT$1,272.4bn leaves roughly NT$1,002.6bn of free cash flow (inferred). Working capital is not a drag: receivables ran at 29 days and inventory at 87 days in Q2 2026, and customers advance cash — NT$189.9bn of temporary receipts sat on the FY2025 balance sheet, with NT$146.6bn due within a year.

The balance sheet carries net cash. Cash and current marketable securities of NT$3,068.6bn at end-FY2025 exceed long-term debt of NT$1,033.0bn, and by Q2 2026 the cash position had reached NT$3,518.0bn, about US$110bn. Debt is used opportunistically rather than structurally: NT$86.9bn of new NT dollar bonds were issued in FY2025 at fixed rates of 0.41% to 4.63%, with maturities out to 35 years.

Where the cash went

Over FY2023–FY2025, capital expenditure absorbed NT$3,178.2bn, dividends NT$1,121.6bn, and share repurchases NT$3.1bn — a single NT$3.1bn purchase in 2024 whose shares were cancelled. Debt was broadly refinanced rather than reduced. In ranking, that is roughly 74% capex, 26% dividends, and a rounding error of buybacks.

The ranking tells you how management thinks, and two constraints shape it. Capital allocation is overwhelmingly reinvestment, and the dividend has become a genuine second claim — quarterly dividends rose 55.6% over six quarters, from NT$4.50 to NT$7.00 per share, with the total distribution reaching NT$181.5bn for Q1 2026. Buybacks are effectively unavailable: the ROC Company Act restricts share repurchases, and the CHIPS Act direct funding agreement adds a five-year buyback restriction. Government grants are material and easy to overlook — NT$76.3bn received in FY2025 from the United States, Germany, Japan and China, roughly 6% of that year’s capital expenditure.

Transactions that post-date the reported figures

Three items sit after the FY2025 20-F and change the picture. TSMC raised its FY2026 capital budget to US$60–64bn from US$52–56bn (Q2 2026 call, 16 July 2026), allocating 70–80% to advanced process technology and 10–20% to advanced packaging, testing and mask making. In August 2026 TSMC signed a binding agreement with Sony to establish Advanced Vision Semiconductor Manufacturing Corporation in Kumamoto for advanced image sensors, with production from 2029; Sony contributes roughly JPY 465bn and consolidates the venture, TSMC roughly JPY 282bn phased by demand and premised on Japanese government support (6-K 2026-08-11). And TSMC Arizona’s board resolved a capital increase of up to US$20bn from the parent in May 2026 (6-K 2026-05-12). None of these appear in the FY2025 reported figures.

6. Cyclicality, Constraints & What to Monitor

TSMC is at, or above, its own prior cyclical peak on every dimension that matters. Gross margin of 67.7% in Q2 2026 exceeds the previous decade peak of 59.6% in FY2022 and sits 21.7 points above the FY2019 trough of 46.0%. Revenue per wafer at NT$253.6 thousand in FY2025 is an all-time high and 2.57 times the FY2016 level. Wafer shipments of 15,022 thousand in FY2025 finally exceeded the FY2022 record of 15,253 thousand only marginally — volume is near, not above, prior peak. A record margin at a peak and a record margin at a trough are opposite facts, and this is unambiguously the former.

What makes 2026 unusual is that there is no single semiconductor cycle to point at. Three of them are running in different directions at once, and TSMC touches all three.

• Leading edge: supply-constrained peak. TSMC’s 5nm-and-below capacity is reported fully utilised through end-2026 with price increases taken across those nodes (TrendForce, 19 March 2026). Packaging is tighter still, with TSMC’s CEO stating that packaging capacity is limiting customers’ growth.
• Mature nodes: mid-recovery, not peak. Eight-inch utilisation across the top ten foundries reached 88% in 2026 heading toward 90%, with three rounds of price increases documented (TrendForce, 30 June 2026). UMC ran at 85% utilisation in Q2 2026. Automotive and industrial demand, weak for two years, has turned: STMicroelectronics reported automotive up 16% and industrial up 34% year over year in Q2 2026.
• Smartphones: record unit contraction. IDC forecasts 2026 shipments just above 1 billion units, down 16.7% — the steepest annual decline on record — caused not by demand but by NAND and DRAM costs up more than 300% year over year, with the sub-US$100 segment being eliminated. Market value still rises 6.3$581 average selling price. For TSMC this is a units-down, mix-up market: bad for mature-node volume, closer to neutral for leading-edge SoC wafers. It is also an unexpected transmission channel, in which the AI boom damages TSMC’s second-largest end market through a segment TSMC does not serve.

The downside mechanism

A downturn would arrive through fixed costs meeting a five-year depreciation schedule. TSMC will spend US$60–64bn in 2026, most of it on equipment depreciated over five years. That charge lands regardless of utilisation. If AI accelerator orders were to pause — and the demand behind them is guided capital expenditure by roughly five buyers, not a diversified end market — revenue would fall against a cost base that had just stepped up. FY2019 is the template: revenue grew 3.6% while gross margin fell 2.3 points and operating margin fell 2.4 points, because the fixed base had been built for a volume that did not arrive.

Two near-term margin headwinds are already disclosed and are not cyclical. TSMC guides overseas-fab dilution of “2% to 3% in the early stages” widening “to 3% to 4% in the latter stages” over the next several years, and a further roughly 3–4 percentage points of dilution in the second half of 2026 from the steep N2 ramp (Q2 2026 call). Against a stated long-term expectation of “56% and higher through the cycle” (Q4 2025 call), the Q2 2026 result of 67.7% carries about eleven points of cushion, some of which management has already told the market it intends to spend.

Physical constraints are real but so far modest in effect. A Q1 2025 earthquake cost NT$5.3bn net of insurance, following NT$3bn in Q2 2024. Utility costs are flagged qualitatively with no quantified impact (unknown). TSMC does not disclose a capacity utilisation rate, which was last published in the FY2020 20-F at 94% — that disclosure has been withdrawn, not merely absent.

Durable versus borrowed

Leading indicators, and where they are published

7. Risks, Unknowns & Questions for Deeper Work

Cyclicality is covered in Section 6. What follows is what cyclicality does not capture, ordered by how badly each would compound with the others.

• Customer concentration is tightening at exactly the point of maximum operating leverage. TSMC’s ten largest customers were 78% of FY2025 revenue, up from 70% two years earlier; the largest was 19% and the second 17%, so two customers are 36% of the company (FY2025 20-F). HPC reached 66% of revenue in Q2 2026. TSMC names the mechanism itself: system companies designing their own semiconductors mean “shifting business models could lead to significant variations in our sales if the growth of their products and services, particularly in the AI sector, is volatile or not sustainable.” A single hyperscaler moving an accelerator programme in-house, or pausing one, removes wafer volume that the fixed cost base cannot follow.
• Geographic concentration cannot be diversified away on any relevant timescale. Nine of TSMC’s sixteen fabs plus headquarters and process R&D sit in three Taiwanese science parks. The mitigation — Arizona, Kumamoto, Dresden — takes a decade and arrives at a worse cost structure, and Taiwan’s own policy may cap what technology can leave. The state of Taiwan’s N-1 rule as of September 2026 could not be established from any source (unknown), and it determines whether an overseas fab can ever run the leading node.
• Export-control liability is structural, not procedural. TSMC states that its position in the supply chain “inherently limits our visibility into the downstream use or user of final products,” and disclosed that in October 2024 it notified US and Taiwan authorities that a customer chip it manufactured “might have been diverted to a restricted entity” (FY2025 20-F). A foundry cannot verify end use it never sees, so this exposure recurs with every customer rather than resolving once.
• Overseas margin dilution is permanent rather than transitional. Management guides 2–3 percentage points of dilution early, widening to 3–4 later. The widening is the tell: as Arizona scales from one fab to three, Japan from one to two, and Dresden comes online, the higher-cost base grows as a share of the whole. This is not a ramp cost that amortises away.
• Government support carries conditions that constrain capital allocation. TSMC received NT$76.3bn of grants in FY2025 and has up to US$6.6bn of CHIPS direct funding, up to US$5bn of US government loans, and up to EUR5bn of German state aid committed. Against that, TSMC guarantees TSMC Arizona’s obligations to the Commerce Department, accepted a five-year buyback restriction, and flags “non-receipt, delay and potential clawbacks of government grants” in its own risk factors. The subsidy is real; so is the loss of freedom.
• Antitrust and political scrutiny scale with success. TSMC writes that “with our success in the foundry business and the increasing criticism on the concentration of the semiconductor industry and sometimes directly on us, we are subject to heightened risks of antitrust investigations” (FY2025 20-F). At 70%-plus of foundry revenue and 86%-plus of the leading edge, this is a slow-moving but one-directional risk.
• A live ITC patent action could reach exclusion orders. Longitude Licensing and Marlin Semiconductor filed complaints in February 2025 alleging that TSMC and its customers infringe five US patents; the ITC instituted an investigation on 21 March 2025 and the parallel Texas case is stayed. TSMC states the outcome cannot be determined and no reliable estimate of contingent liability can be made (FY2025 20-F). The ITC’s remedy is import exclusion, which reaches customers rather than only damages.

What the sources could not answer

• TSMC has never disclosed an absolute average selling price or revenue per wafer; every figure of that kind in this memo is inferred from reported revenue and shipment volumes.
• Capacity utilisation is no longer disclosed. The last published figure was 94% in the FY2020 20-F; the five-year selected-data table was dropped from the FY2021 filing onward.
• No CoWoS or advanced-packaging capacity, revenue contribution, or dedicated capital allocation is disclosed. Everything in Section 3 on packaging capacity comes from TrendForce, not from TSMC.
• Total committed investment in Arizona and in JASM does not appear in the FY2025 20-F; only aggregate grants received. The widely cited US$165bn and US$265bn Arizona figures could not be traced to a TSMC filing.
• The operative state of Taiwan’s N-1 overseas technology rule could not be established; three sources conflict and none is newer than April 2025.
• A16 timing is contradictory: TSMC said volume production was on track for the second half of 2026 on its Q4 2025 call, while trade press reporting from the April 2026 technology symposium put the ramp in 2027. TSMC did not address A16 on either the Q1 or Q2 2026 calls.
• Samsung Foundry’s standalone profitability is not disclosed by Samsung, and no all-segment leading-edge market share split by vendor could be sourced — Counterpoint’s 86% figure is anchored on smartphone SoCs.
• The research folder contains no quarterly earnings release after Q1 2020; all Q1 and Q2 2026 figures in this memo come from TSMC’s investor relations site rather than the archive.

What would need resolving before forming a thesis

Three questions, in order of consequence. First, how much of HPC revenue is training capacity being built ahead of monetised demand, which requires working from the hyperscalers’ disclosures rather than TSMC’s. Second, what gross margin looks like at trough utilisation with the FY2026 capital expenditure fully in the depreciation base — a question the 56%-and-higher statement answers only in management’s own words. Third, whether the Taiwan concentration is priced as a risk or as a certainty, which turns on the N-1 rule and on how quickly Arizona can reach the leading node.

8. Investor Takeaways

• What this business really is: a toll on the leading edge of transistor manufacturing, collected one 12-inch wafer at a time, from customers who have no qualified alternative at 2nm.
• The economic engine: revenue per wafer, not wafers. Volume grew 1.56 times over the decade while price and mix grew 2.57 times — and the margin on that mix runs through a largely fixed cost base.
• The main growth lever: AI and high-performance computing, now 66% of quarterly revenue, resting on the capital budgets of roughly five buyers.
• What could break the story: not a competitor arriving, but the same fixed-cost leverage running backwards — a step-up to US$60–64bn of capex, depreciated over five years, meeting a pause in accelerator orders. Concentration in two customers and one island compounds it.
• What to monitor: gross margin against the 56%-and-higher through-cycle statement, the 2nm share of wafer revenue, and hyperscaler capital expenditure guidance — the last of which moves first.